Integrated circuits have been in existence for around half a century. With the development of technologies, various integrated circuit technologies have been proposed. Chips fabricated with integrated circuits have been widely applied in various different products.
During the chip design or manufacturing process, chips may fail due to various different reasons. As a result, in the chip manufacturing process, chips need to be tested. If it is determined that a chip fails during any stages of the manufacturing process, subsequent production processes of the chip are stopped so as to prevent the manufacturing cost from increasing due to wasted labor.
Wafer testing is usually conducted by conducting probe-test on each chip on a wafer. A test instrument uses a test probe to contact bonding pads on the chip and transmit a particular test signal to the chip under test. The test instrument receives a system response from the chip and compares the system response with an ideal response.
However, it takes test time for the test instrument to transmit the particular test signal to and read the response from the chip under test. The greater the number of chips the need to be tested on a wafer is, the more the time will be spent in testing the chips on the wafer. The use of parallel testing can reduce the total test time. In addition, the test instrument requires signal channels for transmitting signals to and receiving signals from the chips. For a common setting of parallel testing, substantially identical or similar data transmitted into each chip under test, and such substantially identical or similar data may be transmitted in parallel. Nonetheless, the reception of particular signals requires each chip under test be configured with a separate channel. In many cases, the number of signal channels of the test instrument limits the maximum number of chips that may be tested in one parallel test.